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[ CourseLala.com ] Udemy - Verilog HDL Fundamentals for Digital Design and Verification

CourseLalaUdemyVerilogFundamentalsDigitalDesignVerification

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收录时间：2025-08-23

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文件列表：

  1. ~Get Your Files Here !/12. Verilog Design Examples/5. Action Time - Design a Stream Cypher.mp4112.94 Mb
  2. ~Get Your Files Here !/12. Verilog Design Examples/3. Action Time - Data Transfer FSM.mp4108.76 Mb
  3. ~Get Your Files Here !/11. Verilog State Machines/3. Action Time - Special Semaphore (Mealy FSM).mp4103.04 Mb
  4. ~Get Your Files Here !/12. Verilog Design Examples/2. Action Time - Synchronous FIFO.mp478 Mb
  5. ~Get Your Files Here !/11. Verilog State Machines/2. Action Time - Metro turnstile (Mealy FSM).mp470 Mb
  6. ~Get Your Files Here !/9. Verilog Functions and Tasks/14. Action Time - ALU self-checking testbench.mp459.38 Mb
  7. ~Get Your Files Here !/10. Verilog Memory Design/2. Action Time - Single Port Async Read SRAM.mp450.98 Mb
  8. ~Get Your Files Here !/7. Verilog Combinational Design/25. Action time - Design an Arithmetical Logical Unit (ALU).mp450.86 Mb
  9. ~Get Your Files Here !/1. Introduction/2. Course overview.mp450.49 Mb
  10. ~Get Your Files Here !/10. Verilog Memory Design/4. Action Time - Dual Port Async Read SRAM.mp449.89 Mb
  11. ~Get Your Files Here !/1. Introduction/1. Welcome!.mp443.64 Mb
  12. ~Get Your Files Here !/8. Verilog Sequential Design/7. Action Time - D_Flip_Flop_sync_rstn.mp442.07 Mb
  13. ~Get Your Files Here !/8. Verilog Sequential Design/14. Action Time - Shift_Reg_PISO.mp439.98 Mb
  14. ~Get Your Files Here !/9. Verilog Functions and Tasks/12. Action Time - Shift Reg PIPO buggy.mp439.8 Mb
  15. ~Get Your Files Here !/8. Verilog Sequential Design/17. Action Time - Linear Feedback Shift Register.mp439.01 Mb
  16. ~Get Your Files Here !/8. Verilog Sequential Design/15. Action Time - Shift_Left_Right_Reg.mp438.64 Mb
  17. ~Get Your Files Here !/10. Verilog Memory Design/5. Action Time - Single Port Sync Read ROM.mp437.72 Mb
  18. ~Get Your Files Here !/8. Verilog Sequential Design/20. Action Time - Nbit updown Counter.mp437.34 Mb
  19. ~Get Your Files Here !/8. Verilog Sequential Design/24. Action Time - Clock Divider by 3.mp436.7 Mb
  20. ~Get Your Files Here !/5. Verilog Design Styles/6. Verilog_Behavioral_style.mp436.23 Mb
  21. ~Get Your Files Here !/4. Verilog Module/1. Verilog Module - the basics.mp434.94 Mb
  22. ~Get Your Files Here !/5. Verilog Design Styles/15. Action Time - 4bit_full_adder structural.mp434.07 Mb
  23. ~Get Your Files Here !/11. Verilog State Machines/1. Discover Finite State Machines.mp433.95 Mb
  24. ~Get Your Files Here !/8. Verilog Sequential Design/12. Action Time - Shift_Reg_SIPO.mp433.59 Mb
  25. ~Get Your Files Here !/7. Verilog Combinational Design/23. Action Time - HEX 7segment decoder.mp432.23 Mb
  26. ~Get Your Files Here !/8. Verilog Sequential Design/21. Action Time - Modulo_N Counter.mp432.11 Mb
  27. ~Get Your Files Here !/11. Verilog State Machines/5. Action Time - Sequence Detector NON Overlaping.mp430.89 Mb
  28. ~Get Your Files Here !/1. Introduction/4. Understand Abstraction Levels.mp430.63 Mb
  29. ~Get Your Files Here !/8. Verilog Sequential Design/2. Action Time - Clocks Generator.mp429.19 Mb
  30. ~Get Your Files Here !/4. Verilog Module/2. Action time - Do your first testbench.mp429.15 Mb
  31. ~Get Your Files Here !/7. Verilog Combinational Design/21. Action Time - demux_4x_nbit.mp429.11 Mb
  32. ~Get Your Files Here !/7. Verilog Combinational Design/13. Action Time - 4to16 binary Decoder.mp428.74 Mb
  33. ~Get Your Files Here !/9. Verilog Functions and Tasks/7. Action Time - Nbit Comparator Function.mp428.22 Mb
  34. ~Get Your Files Here !/11. Verilog State Machines/7. Verilog Mealy FSM Template.mp428.15 Mb
  35. ~Get Your Files Here !/8. Verilog Sequential Design/6. Basics of edge-triggered logic.mp427.91 Mb
  36. ~Get Your Files Here !/10. Verilog Memory Design/1. Basics of Semiconductor Memory.mp426.82 Mb
  37. ~Get Your Files Here !/8. Verilog Sequential Design/11. Action Time - Shift_Reg_PIPO.mp425.82 Mb
  38. ~Get Your Files Here !/12. Verilog Design Examples/4. Basics of Data Ecryption.mp425.62 Mb
  39. ~Get Your Files Here !/8. Verilog Sequential Design/1. Sequential Logic Basics.mp425.44 Mb
  40. ~Get Your Files Here !/7. Verilog Combinational Design/22. Master the Seven Segment Display Decoder.mp425.34 Mb
  41. ~Get Your Files Here !/10. Verilog Memory Design/3. Action Time - Single Port Sync Read SRAM.mp424.78 Mb
  42. ~Get Your Files Here !/8. Verilog Sequential Design/19. Action Time - Nbit Counter.mp423.44 Mb
  43. ~Get Your Files Here !/7. Verilog Combinational Design/14. Action Time - 8to3 Encoder.mp423.36 Mb
  44. ~Get Your Files Here !/12. Verilog Design Examples/1. Discover the First In First Out (FIFO) circuit.mp422.84 Mb
  45. ~Get Your Files Here !/8. Verilog Sequential Design/23. Action Time - Clock Divider Nbit.mp422.72 Mb
  46. ~Get Your Files Here !/7. Verilog Combinational Design/19. Action Time - mux_4x_nbit.mp422.68 Mb
  47. ~Get Your Files Here !/7. Verilog Combinational Design/9. Action Time - Nbit Comparator.mp422.6 Mb
  48. ~Get Your Files Here !/7. Verilog Combinational Design/11. Action Time - Nbit Decoder.mp422.5 Mb
  49. ~Get Your Files Here !/3. Verilog Data Types and Operators/8. Action time - Vectors.mp422.47 Mb
  50. ~Get Your Files Here !/5. Verilog Design Styles/3. Action Time - half adder structural.mp422.46 Mb
  51. ~Get Your Files Here !/6. Verilog Structural Design/4. Discover the Multiplexer.mp422.43 Mb
  52. ~Get Your Files Here !/8. Verilog Sequential Design/10. Discover the Shift Register.mp422.42 Mb
  53. ~Get Your Files Here !/7. Verilog Combinational Design/8. Action Time - Nbit Adder.mp422.21 Mb
  54. ~Get Your Files Here !/9. Verilog Functions and Tasks/1. Verilog Functions Basics.mp421.5 Mb
  55. ~Get Your Files Here !/1. Introduction/5. Discover the Modern Digital Design Flow.mp421.16 Mb
  56. ~Get Your Files Here !/6. Verilog Structural Design/13. Action Time - 1bit_comparator.mp420.69 Mb
  57. ~Get Your Files Here !/8. Verilog Sequential Design/13. Action Time - Shift_Reg_SISO.mp420.35 Mb
  58. ~Get Your Files Here !/7. Verilog Combinational Design/24. How to use digital logic for arithmetic operations.mp420.25 Mb
  59. ~Get Your Files Here !/8. Verilog Sequential Design/18. Discover Synchronous Counters.mp419.96 Mb
  60. ~Get Your Files Here !/2. Install the Simulator/2. Install Intel Quartus Prime Lite and Modelsim.mp419.9 Mb
  61. ~Get Your Files Here !/9. Verilog Functions and Tasks/13. Discover Automated Verification.mp419.87 Mb
  62. ~Get Your Files Here !/7. Verilog Combinational Design/4. Action Time - Adder Tree.mp419.74 Mb
  63. ~Get Your Files Here !/8. Verilog Sequential Design/22. Discover Digital Frequency Dividers.mp419.49 Mb
  64. ~Get Your Files Here !/7. Verilog Combinational Design/1. What is Combinational logic.mp419.41 Mb
  65. ~Get Your Files Here !/3. Verilog Data Types and Operators/6. Action time - Literal values.mp419.33 Mb
  66. ~Get Your Files Here !/7. Verilog Combinational Design/5. Discover Procedural Assignments.mp419.14 Mb
  67. ~Get Your Files Here !/9. Verilog Functions and Tasks/10. Action Time - Verilog Tasks Control Shift Reg.mp419.04 Mb
  68. ~Get Your Files Here !/8. Verilog Sequential Design/3. Types of Sequential Digital Logic.mp419.04 Mb
  69. ~Get Your Files Here !/6. Verilog Structural Design/7. Action Time -1bit_demux.mp418.95 Mb
  70. ~Get Your Files Here !/6. Verilog Structural Design/2. Verilog Built-in_Primitives.mp418.95 Mb
  71. ~Get Your Files Here !/5. Verilog Design Styles/13. Action Time - full_adder behavioral.mp418.68 Mb
  72. ~Get Your Files Here !/2. Install the Simulator/3. Action Time - Hello World using Verilog.mp418.49 Mb
  73. ~Get Your Files Here !/5. Verilog Design Styles/5. Action Time - half_adder dataflow.mp418.29 Mb
  74. ~Get Your Files Here !/7. Verilog Combinational Design/17. Action Time - Priority Encoder2 4to2.mp417.96 Mb
  75. ~Get Your Files Here !/5. Verilog Design Styles/11. Action Time - full_adder structural.mp417.9 Mb
  76. ~Get Your Files Here !/7. Verilog Combinational Design/16. Action Time - Priority Encoder1 4to2.mp417.89 Mb
  77. ~Get Your Files Here !/2. Install the Simulator/1. Discover the Verilog Simulation.mp417.55 Mb
  78. ~Get Your Files Here !/8. Verilog Sequential Design/4. Action Time - The D_Latch.mp417.42 Mb
  79. ~Get Your Files Here !/5. Verilog Design Styles/16. Action Time - 4bit_full_adder dataflow.mp417.3 Mb
  80. ~Get Your Files Here !/1. Introduction/3. What is Verilog HDL.mp417.27 Mb
  81. ~Get Your Files Here !/3. Verilog Data Types and Operators/4. Action time - Multiple procedures.mp417.19 Mb
  82. ~Get Your Files Here !/7. Verilog Combinational Design/15. What is a Priority Encoder.mp416.69 Mb
  83. ~Get Your Files Here !/3. Verilog Data Types and Operators/29. Action Time - Replication Operator.mp416.68 Mb
  84. ~Get Your Files Here !/6. Verilog Structural Design/5. Action Time - 1bit_mux.mp416.58 Mb
  85. ~Get Your Files Here !/8. Verilog Sequential Design/5. Action Time - D_Latch_reset_n.mp416.49 Mb
  86. ~Get Your Files Here !/12. Verilog Design Examples/6. Congratulations!.mp416.48 Mb
  87. ~Get Your Files Here !/7. Verilog Combinational Design/6. Action Time - Tree Adder Procedural.mp416.35 Mb
  88. ~Get Your Files Here !/4. Verilog Module/6. Action Time - Generate Waveforms.mp416.12 Mb
  89. ~Get Your Files Here !/9. Verilog Functions and Tasks/5. Action Time - Verilog Functions Factorial.mp415.7 Mb
  90. ~Get Your Files Here !/3. Verilog Data Types and Operators/3. Hardware Description Language data types.mp415.7 Mb
  91. ~Get Your Files Here !/8. Verilog Sequential Design/8. Action Time - D_Flip_Flop_async_rstn.mp415.55 Mb
  92. ~Get Your Files Here !/8. Verilog Sequential Design/16. Discover the Linear Feedback Shift Register.mp415.48 Mb
  93. ~Get Your Files Here !/6. Verilog Structural Design/6. Discover the Demultiplexer.mp415.41 Mb
  94. ~Get Your Files Here !/7. Verilog Combinational Design/10. Differentiate between binary encoders and decoders.mp415.4 Mb
  95. ~Get Your Files Here !/3. Verilog Data Types and Operators/1. Verilog Data types overview.mp415.37 Mb
  96. ~Get Your Files Here !/9. Verilog Functions and Tasks/4. Discover Verilog Recursive Functions.mp415.27 Mb
  97. ~Get Your Files Here !/3. Verilog Data Types and Operators/15. Action Time - Logical Operators usage.mp415.11 Mb
  98. ~Get Your Files Here !/6. Verilog Structural Design/11. Action Time - mux_tri-state.mp415.03 Mb
  99. ~Get Your Files Here !/3. Verilog Data Types and Operators/2. Action time - sum and product.mp415.01 Mb
  100. ~Get Your Files Here !/5. Verilog Design Styles/10. Design a 1bit full_adder.mp414.62 Mb
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